Sanjay ( Naperville Central H.S.)
Mentor: Ted Lui
The Compact Muon Solenoid (CMS) is one of two multi-purpose detectors at CERN that are used to try to detect evidence of new physics, including the Higgs boson and dark matter particles. Inside this detector, bunches of protons are collided with each other, resulting in many 'events.' In order to isolate the interesting events from unwanted 'pileup' events, scientists require technology that will be capable of processing information at very high speeds. At Fermilab, physicists and engineers interested in solving this problem have been collaborating on hardware-based pattern recognition technology called Vertically Integrated Pattern Recognition Associative Memory (VIPRAM). In this study, we present results from rigorous testing of a 2D prototype chip, highlighting and exploring possible causes of error in the chip's ability to match and reject patterns. The primary cause of errors is excessive power consumption. We also test the chip on real data patterns and optimize the chip's performance on these patterns based on knowledge about how power consumption in the chip works. In the future, we will extend testing to include information about performance-dependence on voltage and specific power consumption measurements. VIPRAM technology will continue to be improved with the production of a 3D prototype being a major future step in the development of the chip.